The present invention generally relates to a wafer-scale semiconductor device, and more particularly to an improvement in a system configuration directed to mutually connecting functional blocks such as memory chips on a wafer so as to avoid a defective functional block (memory chip) being connected.
Recently, there has been considerable activity in the development of a wafer-scale semiconductor integrated memory device. Referring to FIG. 1, there is illustrated the entire structure of a wafer-scale semiconductor memory device and one of a plurality of memory chips formed on a wafer 1. The memory chips (memory circuits) 2 are mutually connected through a communication path (interconnection line) 3 connected to a data input/output terminal 4 in such a way that defective memory chips 5 illustrated by blocks with crosses are not connected.
Each of the memory chips 2 is made up of a storage circuit 2a formed of a DRAM (dynamic random access memory), a write/read control logic circuit 2b labeled CONLOG2, a configuration logic circuit 2c labeled CONLOG1 and a switching transistor QA. Hereinafter, the configuration logic circuit 2c and the write/read control logic circuit 2b are simply referred to as first and second logic circuits 2c and 2b, respectively. A positive power supply line Vcc is connected to the DRAM 2a via the switching transistor QA, which is formed of, for example, a P-channel MOS transistor. The DRAM 2a is directly connected to negative power supply lines Vss and Vbb, respectively. The positive power supply line Vcc is also connected to the second logic circuit 2b via the switching transistor QA. The first logic circuit 2c inputs data and commands supplied from an adjacent memory chip via a bus and outputs data and commands thereto via the bus. The second logic circuit 2b mutually couples the DRAM 2a and the first logic circuit 2b. The source and drain of the switching transistor QA of the P-channel type are connected to the positive power supply line Vcc and the DRAM 2a, respectively, and the gate thereof is connected to an output terminal of the first logic circuit 2c.
The first logic circuit 2c controls the gate of the switching transistor QA as follows. When the memory chip 2 is connected to the communication path 3, the first logic circuit 2c outputs a low-level gate control signal to the gate of the switching transistor QA in response to an external control signal S. On the other hand, when it is necessary to disconnect the DRAM 2a shown in FIG. 1 due to the presence of a defect in the DRAM 2a, the first logic circuit 2c outputs a high-level gate control signal to the gate of the switching transistor QA in response to the external control signal S. Thus, the switching transistor QA is turned OFF so that the DRAM 2a is electrically disconnected from the positive power supply line Vcc.
There is a possibility that even when the first logic circuit 2c is instructed to turn OFF the switching transistor QA by the external control signal S, the first logic circuit 2c may output the low-level gate control signal to the gate of the switching transistor QA due to a defect of the first logic circuit 2c. For example, a transistor of the first logic circuit 2c may be formed in a substrate containing a defective crystal, which forming may occur during a wafer process. Such a defective transistor may output a reverse logic. Another cause of a malfunction of the first logic circuit 2c may be an interlayer short-circuit in which aluminum interconnection lines which are provided at the different layer levels are short-circuited, so that a reverse output logic occurs.
In cases as described above, the switching transistor QA is maintained ON even if the external control signal S instructs the first logic circuit 2c to disconnect the DRAM 2a having a defect from the positive power supply line Vcc. As a result, a short current passes through the DRAM 2a. Such a short current decreases the power source voltage Vcc which is to be applied to other memory chips and increases the entire power consumption of the device which is in a standby mode. Conventionally, if the first logic circuit 2c is defective, a jump bonding is employed in which bonding wires are provided so as to jump the defective memory chip and connect normal adjacent memory chips which are arranged on both sides of the defective memory chip in the same column of the device. However, it is very difficult to mutually connect two normal memory chips located on both sides of a series of two or more defective memory chips aligned in the column direction.